(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for fabricating concurrently field effect transistors (FETs) having dual dielectric gate electrodes for memory having embedded logic.
(2) Description of the Prior Art
With the advent of Large Scale Integration (LSI) many of the integrated circuits formed on semiconductor substrates are comprised of several circuit functions on a single chip. For example, dynamic random access memory (DRAM), nonvolatile memory (NVM), and similar memory devices are composed of an array of memory cells for storing digital information, while the peripheral circuits on these devices are typically composed of logic circuits for addressing the memory cells, while other peripheral circuits function as read/write buffers and sense amplifiers.
To improve performance and optimize these devices, it is very desirable in the electronics industry to provide FETs that have both thin and thick gate oxides (dielectrics). Typically, a thin gate oxide (dielectric) is used in the peripheral (logic) circuits to enhance FET device performance, while it is desirable to provide a thicker gate oxide for the higher gate voltage (Vg) requirements on the FET access transistors in the DRAM cells. For example, the FETs in the logic circuits would have a gate voltage of about 3.3 volts, while the access transistor in each of the memory cells would require a gate voltage of 7 volts, such as in the boosted word line architecture in which a 5.0 volt difference between the gate electrode and substrate is required to turn on FETs when the substrate has a voltage bias of about 2 volts.
Typically, by the prior art and as shown in the schematic cross-sectional view in FIG. 1, the dual-gate oxide is formed by thermally growing in the memory cell device area 2 and in the logic device area (peripheral area) 4 a first gate oxide 14 on the substrate 10 having a field oxide (FOX) 12. A photoresist mask 16 is then used to mask the gate oxide 14 over the memory cell device area 2, and the gate oxide 14 is etched in the logic device area 4. FIG. 1 shows the structure prior to etching the gate oxide 14. The photoresist is then stripped and a second gate oxide 18 is grown on the logic device area 4, while the original gate oxide 14 (depicted by the dashed line 14) in the memory cell device area 2 increases in thickness as shown in FIG. 2. Unfortunately, by the method of the prior art, the presence of the photoresist over the gate oxide 14 in the memory device area contaminates the oxide and degrades the device electrical characteristics. For example, one such contaminant is the mobile sodium (Na) ion in the gate oxide that can and does affect the long-term stability of the gate voltage (Vg) on the FET.
Therefore, there is still a strong need in the semiconductor industry for providing a thin gate oxide for the logic areas, and a thicker gate oxide for the memory areas without having the photoresist layer come into direct contact with the gate oxide, and by a method that does not substantially increase the manufacturing process complexity or cost.